The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a FinFET CMOS device and method for fabricating a FinFET CMOS device with NVRAM capability.
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
Data is stored in memory. In general, memory can be Read Only Memory (ROM) or RAM, Random Access Memory. Most RAMs, including DRAM and SRAM, are volatile. That is, when power is removed, the data contained in the DRAM or SRAM cells are lost. Non-Volatile Random Access Memory or NVRAM is memory which retains its data contents despite power failure. Examples of NVRAM include FLASH, electrically erasable reprogrammable read-only memory or EEPROM and electrically programmable read-only memory or EPROM.
NVRAM has been accomplished by the incorporation of a floating gate structure into the transistors of memory devices. Floating gates are comprised of conductive material which is electrically insulated from surrounding structures. A floating gate may be placed between gate insulator material and a second gate where the second gate may be a control gate. Floating gates can be charged using tunneling techniques (sometimes referred to as Fowler-Nordheim tunneling) where a large voltage is applied between the control gate and the substrate resulting in a charge accumulating in the floating gate, or another technique well known in the art, hot-electron programming. Once the floating gate has been charged, because the floating gate is electrically isolated in the circuit, that charge remains intact without the requirement of being refreshed. The level of charge accumulation in floating gate structures can be carefully controlled. Floating gate structures have been used to implement neural-network-type hardware.
Previously, the incorporation of floating gate structures into the transistors of memory devices has been accomplished using traditional semiconductor fabrication techniques to build traditional FET structures. However, the need to remain cost and performance competitive requires that these floating gate structures be incorporated into semiconductor devices in higher densities to allow for the reduction in size of semiconductor devices. Thus, there is a need for improved device structures and methods of fabrications of floating gates that provide NVRAM capability in smaller devices.
It is thus an object of the present invention to provide NVRAM capability for high density semiconductor devices.
In one aspect, the present invention an NVRAM comprises the steps of providing an SOI wafer and defining a Fin on the SOI wafer; providing gate insulator on at least one vertical surface of the Fin; depositing floating gate material over the gate insulator; depositing insulator material on the floating gate material to form the floating gate isolation; depositing control gate material over the isolated floating gate material; removing a portion of the control gate material to expose source and drain regions of the Fin, and implanting to form source/drain regions in the exposed regions of the Fin.
In another aspect, the invention is an NVRAM device comprising a transistor body having two sides; a gate insulator on both of the sides of the transitor body; and first and second floating gates on said gate insulator and disposed on respective sides of said transistor body.